I. Field of the Invention
This invention relates generally to semiconductor devices utilizing inverted vertical bipolar transistors having two or more collectors. More specifically, the invention relates to an improvement in device structure for the control of collector gain.
II. Description of the Prior Art
Vertical bipolar transistors are well known and widely used in bipolar integrated circuit structures. The use of vertical NPN's is generally preferred for high speed applications because the electron mobility in NPN's is greater than the hole mobility in PNP's. Inverted or upside down vertical bipolar transistor structures having multiple collectors disposed above a common emitter are known and have frequently been used to accomplish logic functions. Such structures can be realized by using a buried layer as the common emitter and forming individual collectors in the surface of an epitaxial layer. This structure is taught in U.S. Pat. No. 3,244,950 issued to J. P. Ferguson on Apr. 5, 1966, and entitled "Reverse Epitaxial Transistor."
Interest in inverted vertical bipolar transistors has increased with the advent of a radically different but remarkably simple form of bipolar logic called Integrated Injection Logic or Merged Transistor Logic. Integrated Injection Logic (commonly abbreviated I.sup.2 L) reduces a logic gate to a merged complementary transistor pair. In such a merged structure, a lateral PNP transistor is generally used as the current source for the base of an inverted vertical bipolar transistor having multiple collectors. The orgin of this logic concept is found in two papers delivered to the IEEE International Solid-State Circuits Conference in Feb. 1972. See H. H. Berger and S. K. Wiedmann, "Merged Transistor Logic (MTL) -- A Low-Cost Bipolar Logic Concept," Digest, 1972 ISSCC, pp. 90-91, Journal of Solid-State Circuits, Vol. SC-7, 1972, pp. 340-346, and K. Hart and A. Slob, "Integrated Injection Logic: A New Approach to LSI", Digest, 1972 ISSCC, pp. 92-93, Journal of Solid-State Circuits, Vol. SC-7, 1972, pp. 346-351. As described in these articles, Integrated Injection Logic possesses the inherent advantage of being able to reduce the size of circuit elements since gates are reduced to a single device format, possesses an inherently low propagation-delay power product as a result of low operating voltage and capacitance, and can generally be fabricated with as few as five masks.
Oxide-isolated semiconductor devices are known to provide sufficient advantages over junction-isolated or cut-and-fill-isolated devices. The employment of Isoplanar Oxide-isolation, as taught in U.S. Pat. No. 3,648,125 issued to D. L. Peltzer on Mar. 7, 1972, entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure", accomplishes the objective of inter-device isolation, achieves high packing densities, reduces sidewall capacitances and reduces direct current losses for vertical bipolar transistors. The fabrication of oxide-isolated Integrated Injection Logic Structures is taught in a U.S. Pat. No. 3,962,717, issued to David O'Brien on June 8, 1976 and entitled "Combined Method for Fabricating Oxide-Isolated Lateral Bipolar Transistors and the Resulting Structures." The Ferguson patent, the Peltzer patent and the O'Brien patent are all assigned to and owned by the assignee of the present application.
A recent, quite readable overview of the present state of integrated injection logic technology can be found in a companion pair of articles by H. H. Berger and S. K. Wiedmann entitled, "The Bipolar LSI Breakthrough, Part I: Rethinking the Problem", Electronics, Sept. 4, 1975, pp. 89-95 and "The Bipolar LSI Breakthrough, Part II: Extending the Limits", Electronics, Oct. 2, 1975, pp. 99-103.
Most I.sup.2 L devices characteristically exhibit an almost linear speed-power product over a wide range of operating currents, but flatten out at high currents. When higher currents are employed to achieve higher speed, the series resistance in the base of the vertical bipolar transistor impedes the lateral current flow from the injector to the multiple collectors. The further a collector is located from the source of base current, the more adversely it is affected by the series resistance. When a plurality of I.sup.2 L gates are interconnected to form a logic function, each collector of a multi-collector transistor must be able to short one base current. This means that the current gain per collector must be greater than or equal to unity (if all base currents are assumed equal). As the base current is increased to achieve higher operating speeds, the gain of those collectors most distant from their associated source of base current falls below unity because of the base series resistance described above thereby limiting the maximum speed of the circuit.